1. Field of the Invention
This invention relates to a Schmitt circuit which is used as input circuits for, for example, MIS (insulated gate) type semiconductor integrated circuits and, in particular, the Schmitt circuit in which MIS type field effect transistors are used.
2. Description of the Prior Art
FIG. 1 shows a conventional example of this kind of Schmitt circuit. That is to say Q1, Q2, Q3 an Q4 are all N channel MIS type (for example, MOS type) field effect transistors. Of these, Q2, Q3 and Q4 are enhancement type (E type) and Q1 is depletion type (D type). The drain of said D type transistor Q1 is connected to the VDD power source node while its gate and source are connected to each other. Between this common connection point N2 and the VSS potential terminal (the earth potential terminal), E type transistors Q2 and Q3 are connected in series. The gates of transistors Q2 and Q3 are connected together and this point is the signal input node N1. The common connection point N2 is the signal output node. The E type transistor Q4 is connected between the VDD power source node and the point A where the source and drain of transistors Q2 and Q3 are connected together. The gate of transistor Q4 is connected to output node N2.
Concerning the operation of an MIS type Schmitt circuit, as is well known, it operates as an inverter circuit in which the circuit threshold voltage differs when the input signal voltage for input node N1, rises and when it falls. Here, when taking the input signal as .phi..sub.IN, the output signal of output node N2 as .phi..sub.OUT, the circuit threshold voltage when the input voltage rises as VON and the circuit threshold voltage when the input voltage falls as VOFF, the input/output curve possesses a hysteresis characteristic as shown in FIG. 3. That is to say, in the case of the input voltage when it changes in the higher voltage direction but is lower than the circuit threshold voltage VON when the input voltage rises, transistor Q2 is OFF, and a high (H) level output voltage (=VDD) appears at output node N2 from the VDD power source node via transistor Q1. At this time, transistor Q4 is ON and potential VA at connection point A is approximately potential VDD or the level determined by the ratio of the conducting resistances of transistors Q4 and Q3. When the input voltage changes in the higher voltage direction and exceeds voltage VON, transistors Q2 and Q3 are respectively ON and output signal .phi..sub.OUT is low (L) level which is determined by the ratio of the conducting resistance of transistor Q1 and the conducting resistances of transistors Q2 and Q3. At this time transistor Q4 is OFF and the connection point potential VA is almost earth potential. Next, when the input voltage changes in the lower direction, the conduting resistances of Q2 and Q3 rise in conjunction with this and so the voltage of output signal .phi..sub.OUT rises and transistor Q4 is in the ON position. Because of this, connection point potential VA rises and causes the conducting resistance of transistor Q2 to increase, and the potential of output signal .phi..sub.OUT and connection point potential VA rise further. When this voltage VA has risen to a certain value, transistor Q2 takes the OFF position and the potential of output signal .phi..sub.OUT reaches the H level of VDD potential. The voltage of input signal .phi..sub.IN at this time is the circuit threshold voltage VOFF when the input voltage falls.
In this way, from the fact that connection point potential VA differs according to the rising and falling of the input voltage, the circuit threshold value VON when the input voltage rises differs from circuit threshold value VOFF when the input voltage falls, and therefore the relationship VON&gt;VOFF is established.
In the conventional MIS type Schmitt circuit described above, the circuit threshold value VON when the input voltage rises depends on the potential of connection point A which is determined by the ratio of the conducting resistance of transistor Q3 and that of Q4, and the circuit threshold value VOFF when the input voltage falls depends on the potential of connection point A which is determined by the ratio of the conducting resistances of transistors Q2 and Q3 and the conducting resistance of transistor Q1 which is its load element. The VDD power source voltage dependencies of the voltages VON and VOFF are shown in FIG. 4. The power source voltage dependency of voltage VOFF is comparatively small, but the power source voltage dependency of voltage VON is large.
Therefore, in the case, for example, of using an MIS type Schmitt circuit in the external signal input circuit of an MIS semiconductor integrated circuit, there is a problem in that when, as described above, there is a large power source voltage dependency in its circuit threshold values VON and VOFF, the speed of operation of the integrated circuit's inner circuit reduces. In the case where the operating mode of the inner circuit is specified by the timing relationships of multiple input signals, since it is difficult to grasp the timing relationships accurately, this causes great obstacles. That is to say, when taking account of fluctuation of the power source voltage, the fluctuation margin in the mutual timing relationships of multiple input signals is small.